1. Field of the Invention
This invention relates to the field of high speed information processing systems, and in particular to a memory interface for synchronous memories which provides high speed access.
2. Description of the Related Art
The demand for high performance communications and information processing systems is driving the clock rates of these systems higher. The increase in processor speeds is being followed by an increase in system bus speeds and increases in memory speeds. Two main types of memories exist: DRAMs and SRAMs. DRAMs (dynamic random access memories) are the most common kind of random access memory for personal computers and workstations. DRAMs consist of a network of capacitors upon which are stored electric charges representing binary 0's and 11's. Since the amount of charge is very small, each of the capacitors must have its charge refreshed every few milliseconds to prevent the data from being lost. Due to the small size of the charges, very accurate sensing circuits are provided for detecting the stored data. The access speed of DRAMs is largely limited by the sensing circuitry.
SRAMs (static random access memories) are typically used for data caches or high performance memory applications due to their higher speed and higher cost. SRAMs consist of a network of flip-flops which actively latch a voltage state at a given node. Since the flip-flops are powered, the memory accesses to SRAMs is much faster than to DRAMs.
Various architectural adaptations of SRAMs and DRAMs have been made in the last few years to reduce memory access times. These adaptations include: providing on-chip memory control circuitry, using clocked inputs, pipelining memory accesses, and using latches to provide relaxed timing constraints. These adaptations allow access to sequential memory locations faster than the underlying memory technology would otherwise support. When accompanied by improvements in the memory technology in the form of improved processing and reduced cell sizes, the memories are becoming very fast indeed.
A memory known as Synchronous burst SRAM has recently been developed. Unlike asynchronous SRAM in which reads and writes are performed in a sequential fashion, with one operation completed before the next begins, Synchronous burst SRAM allows a second data access to begin before the first is completed. This allows burst transfer rates as high as 100 MB per second. The chip is designed to take in an address on the rising edge of the clock. The address and certain control information are latched on the clock edge. The latch drives the address decoders, which drive the memory array, and 9 ns or so later, data is available. The chip may include an internal burst counter so it can provide consecutive words of data in response to one address cycle. Some versions of the chip are provided with an output data latch which adds an initial access cycle but relaxes timing constraints on the chip.
The access time for the first word of data is two cycles (three for the versions with the output latch), and subsequent data words are available at one cycle intervals thereafter. Whenever the data flow is interrupted, an additional cycle or two is required to get it restarted. This may prove harmful to the system performance if interruptions are frequent, particularly to systems requiring high data bandwidths such as communications systems. A method for avoiding the repeated loss of initial access cycles would be beneficial to these systems, and is therefore desirable.